Quantification of surface state effects in GaAs MESFETs

The operation of gallium arsenide schottky barrier field effect transistor is greatly affected by several anomalies such as frequency dispersion of output impedance, zds; this low frequency behaviour is related to the presence of capture centres at the channel/substrate interface. In this context, we investigate the influence of such defects via a circuit consisting of a capacitance in series with a resistance placed in parallel to the output of a transistor, between drain and source. Then, using PSPICE program we made some simulations at several bias of the device and different values of elements characterising traps. It was found that the dispersion increases when the value of the drain bias increases. It was also shown that the dispersion increases with increasing trap resistance. Whereas, the trap capacitance greatly affects the initial and final saturation of the output impedance